The present invention relates to a flip-flop circuit for, e.g., constituting a counter.
It is well known that a dynamic RAM requires refreshing of storage data. FIG. 1 partially shows a refresh control circuit of a dynamic RAM. The memory cells of the dynamic RAM are arranged in a matrix on a semiconductor chip, and constitute memory cell array 10 shown in FIG. 1. The rows of array 10 are selected by row decoder 12. In the refresh mode, the content of the memory cells in the selected row is updated to new data having the same logic value as that of old data. The refresh control circuit has address counter 14, which causes decoder 12 to sequentially designate row addresses of array 10. Address counter 14 comprises series-connected register stages 14-1 to 14-N. The output terminals of register stages 14-1 to 14-N are parallel-connected to row decoder 12 to supply a refresh address signal thereto. Enable signal EN shown in FIG. 1 is supplied to register stages 14-1 to 14-N in the refresh mode. Clock signals .phi.0 and .phi.0 have a complementary relationship therebetween, and are supplied to register stage 14-1. For example, register stage 14-1 generates output signal .phi.1 shown in FIG. 2B in response to the trailing edge of clock signal .phi.0 shown in FIG. 2A. Register stage 14-2 generates output signal .phi.2 shown in FIG. 2C in response to the trailing edge of clock signal .phi.1 shown in FIG. 2B. More specifically, a refresh address is incremented each time the logic values of clock signals .phi.0 and .phi.0 are inverted. Register stages 14-1, 14-2, . . . must hold the logic values of output signals .phi.1, .phi.1; .phi.2, .phi.2 . . . while the logic values of input signals .phi.0, .phi.0; .phi.1, .phi.1 . . . are not changed and while enable signal EN is not supplied.
Conventionally, each of register stages 14-1 to 14-N has a flip-flop circuit like that shown in FIG. 3 or 4. In the flip-flop circuits shown in FIGS. 3 and 4, the potential of a VDD level (e.g., 5 V) or a VSS level (e.g., 0 V) is set at input terminal IN or IN in accordance with signals .phi.0 and .phi.0. Note that the potentials of input terminals IN and IN have a complementary relationship therebetween, such that when the potential of one terminal changes from the VDD to VSS level, the potential of the other terminal changes from the VSS to VDD level. Enable signal EN is selectively supplied to control terminal CT. The potential of control terminal CT is set at a first level equal to or higher than a (VDD+VTH) level [e.g., the (VDD+VTH) level] when enable signal EN is supplied thereto; otherwise, terminal CT is set at a second level lower than a VTH level (e.g., the VSS level). Note that "VTH" indicates the threshold voltage of n-channel MOS transistors. In the flip-flop circuits shown in FIGS. 3 and 4, n-channel MOS transistors Q1 to Q4 charge or discharge nodes N2 and N1 in accordance with the potentials of input terminals IN and IN, thereby setting one of the potentials of output terminals OUT and OUT at the VDD level and the other thereof at the VSS level. Terminal S receives a pulse signal, which periodically changes from one of the VSS and VDD levels to the other, from a pulse oscillator (not shown). N-channel MOS transistors Q5 and Q7 and MOS capacitor C1 constitute a first potential compensation circuit for compensating for the potential drop of output terminal OUT of node N1, when output terminal OUT is set at the VDD level. N-channel MOS transistors Q6 and Q8, and MOS capacitor C2 constitute a second potential compensation circuit for compensating for the potential drop of output terminal OUT of node N2, when output terminal OUT is set at the VDD level. The potential drops of output terminals OUT and OUT are caused by a drive current of the MOS transistors connected to terminals OUT and OUT as, e.g., loads.
The operation of the flip-flop circuit shown in FIG. 3 will now be described. For example, when MOS transistors Q1 and Q2 are rendered conductive and the potentials of nodes N1 and N2 are respectively set at the VSS and VDD levels, MOS transistors Q3 and Q4 are respectively rendered conductive and nonconductive. The potentials of nodes N1 and N2 are thereby held, even after MOS transistors Q1 and Q2 are turned off. MOS transistor Q8, for example, charges node N4 in response to the leading edge of the potential of the corresponding output terminal OUT. When the potential of node N4 exceeds the (VDD-VTH) level, transistor Q8 is turned off, and node N4 is left charged. The potential of node N4 increases due to its capacitive coupling each time the pulse signal at the VDD level is supplied to capacitor C2, and then exceeds the (VDD+VTH) level. Thereby, MOS transistor Q6 is rendered conductive. If the potential of output terminal OUT is decreased because of a load after it is set at the VDD level, the potential can usually be increased to the VDD level by turning on MOS transistor Q6.
When the potential of node N1 is set at the VSS level, MOS transistor Q7 is conductive. However, since node N3 is not charged by MOS transistor Q7, it cannot turn off transistor Q7. MOS transistor Q5 receives a gate voltage at the VSS level through MOS transistors Q3 and Q7, and is rendered nonconductive regardless of the pulse signal at the VDD level supplied to capacitor Cl at this time. Therefore, the potential of output terminal OUT is maintained at the VSS level.
The flip-flop circuit shown in FIG. 4 has the same arrangement as that in FIG. 3, except in that the gates of MOS transistors Q7 and Q8 are connected to nodes N2 and N1, respectively. Node N3 is charged by MOS transistor Q7 during a transient period in which the potential of node N1 is changed from the VSS to VDD level and the potential of node N2 is changed from the VDD to VSS level. MOS transistor Q7 is rendered completely nonconductive when the potential of node N2 has reached the VSS level, thus storing charges at node N3. At this time, the potential of node N3 is set at about the (VDD-VTH) level, and is further increased by the pulse signal at the VDD level. Node N4 is charged by MOS transistor Q8 during a transient period in which the potential of node N1 is changed from the VDD to VSS level and the potential of node N2 is changed from VSS to VDD level. MOS transistor Q8 is rendered completely nonconductive when the potential of node N1 has reached the VSS level, thereby storing charges at node N4. At this time, the potential of node N4 is set at about the (VDD-VTH) level, and is further increased by the pulse signal at the VDD level. Therefore, MOS transistors Q5 and Q6 are controlled in the same manner as in the flip-flop circuit shown in FIG. 3.
The flip-flop circuits shown in FIGS. 3 and 4 have the following drawbacks. The flip-flop circuit shown in FIG. 3 cannot cope with a large potential drop after the potential at the VDD level is set at one of output terminals OUT and OUT. When the potential of, e.g., output terminal OUT is decreased below the (VDD-VTH) level, MOS transistor Q8 is undesirably rendered conductive, and charges are moved from node N4 to node N2 therethrough. More specifically, MOS transistor Q8 cannot charge node N4 to a level high enough to turn on MOS transistor Q6 with use of the pulse signal at the VDD level. Therefore, the potential of output terminal OUT cannot be restored at the VDD level. This also occurs when the potential of output terminal OUT is decreased below the (VDD-VTH) level.
The flip-flop circuit shown in FIG. 4 cannot cope with a decrease in charges after one of nodes N3 and N4 is charged. For example, when the amount of charge of node N4 is decreased by current leakage or the like, MOS transistor Q6 often cannot be supplied with sufficient gate voltage from node N4. MOS transistor Q8 is turned on or off in accordance with the potential of node N1, and is kept nonconductive by the gate voltage at the VSS level after charges are stored at node N4. Therefore, MOS transistor Q8 cannot charge node N4 when the potential of node N4 is decreased. When node N3 is charged in order to maintain the potential of output terminal OUT at the VDD level, MOS transistor Q7 operates in the same manner as transistor Q8.
As described above, the flip-flop circuits shown in FIGS. 3 and 4 are unsuitable for maintaining an output signal for a long period of time. In these circuits, the potentials of output terminals OUT and OUT cannot be set at specific levels immediately after a power source is turned on, and the potentials of output terminals OUT and OUT depend on the charged states of nodes N1 and N2.